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FEATURES Single-Supply Operation: 2.7 V to 5.5 V Low Supply Current: 45 A/Amplifier Wide Bandwidth: 1 MHz No Phase Reversal Low Input Currents: 4 pA Unity Gain Stable Rail-to-Rail Input and Output APPLICATIONS ASIC Input or Output Amplifier Sensor Interface Piezo Electric Transducer Amplifier Medical Instrumentation Mobile Communication Audio Output Portable Systems
General-Purpose CMOS Rail-to-Rail Amplifiers AD8541/AD8542/AD8544
PIN CONFIGURATIONS 5-Lead SC70 and SOT-23 (KS and RT Suffixes)
OUT A 1 V 2 4 IN A
AD8541
5 V+
+IN A 3
8-Lead SOIC (R Suffix)
NC 1 -IN A +IN A 2 3 4
AD8541
8 7 6 5
NC V+ OUT A NC
GENERAL DESCRIPTION
V-
The AD8541/AD8542/AD8544 are single, dual, and quad railto-rail input and output single-supply amplifiers featuring very low supply current and 1 MHz bandwidth. All are guaranteed to operate from a 2.7 V single supply as well as a 5 V supply. These parts provide 1 MHz bandwidth at a low current consumption of 45 mA per amplifier. Very low input bias currents enable the AD8541/AD8542/AD8544 to be used for integrators, photodiode amplifiers, piezo electric sensors, and other applications with high source impedance. Supply current is only 45 mA per amplifier, ideal for battery operation. Rail-to-rail inputs and outputs are useful to designers buffering ASICs in single-supply systems. The AD8541/AD8542/AD8544 are optimized to maintain high gains at lower supply voltages, making them useful for active filters and gain stages. The AD8541/AD8542/AD8544 are specified over the extended industrial temperature range (-40C to +125C). The AD8541 is available in 8-lead SOIC, 5-lead SC70, and 5-lead SOT-23 packages. The AD8542 is available in 8-lead SOIC, 8-lead MSOP, and 8-lead TSSOP surface-mount packages. The AD8544 is available in 14-lead narrow SOIC and 14-lead TSSOP surfacemount packages. All MSOP, SC70, and SOT versions are available in tape and reel only.
NC = NO CONNECT
8-Lead SOIC, MSOP, and TSSOP (R, RM, and RU Suffixes)
OUT A -IN A +IN A V- 1 2 3 4
AD8542
8 7 6 5
V+ OUT B -IN B +IN B
14-Lead SOIC and TSSOP (R and RU Suffixes)
OUT A -IN A +IN A V+ +IN B -IN B OUT B 1 2 3 4 5 6 7 14 OUT D 13 -IN D 12 +IN D
AD8544
11 V- 10 +IN C 9 8 -IN C OUT C
REV. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD8541/AD8542/AD8544-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V = 2.7 V, V
S CM
= 1.35 V, TA = 25 C, unless otherwise noted.)
Min Typ 1 4 Max 6 7 60 100 1,000 30 50 500 2.7 Unit mV mV pA pA pA pA pA pA V dB dB V/mV V/mV V/mV mV/C fA/C fA/C fA/C V V mV mV mA mA W dB dB mA mA V/ms ms kHz Degrees nV//Hz nV//Hz pA//Hz
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current
Symbol VOS IB IOS
Conditions
-40C TA +125C -40C TA +85C -40C TA +125C -40C TA +85C -40C TA +125C VCM = 0 V to 2.7 V -40C TA +125C RL = 100 kW , VO = 0.5 V to 2.2 V -40C TA +85C -40C TA +125C -40C TA +125C -40C TA +85C -40C TA +125C -40C TA +125C IL = 1 mA -40C TA +125C IL = 1 mA -40C TA +125C VOUT = VS - 1 V f = 200 kHz, AV = 1 VS = 2.5 V to 6 V -40C TA +125C VO = 0 V -40C TA +125C RL = 100 kW To 0.1% (1 V Step) 65 60
Input Offset Current
0.1
Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain
CMRR AVO DVOS /DT DIB /DT DIOS /DT VOH VOL IOUT ISC ZOUT PSRR ISY
0 40 38 100 50 2
45 500
Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Density Current Noise Density
Specifications subject to change without notice.
4 100 2,000 25 2.575 2.550 2.65 35 15 20 50 76 38 55 75 100 125
SR tS GBP Fo en en in
0.4
0.75 5 980 63 40 38 <0.1
f = 1 kHz f = 10 kHz
-2-
REV. D
AD8541/AD8542/AD8544 ELECTRICAL CHARACTERISTICS (V = 3.0 V, V
S CM
= 1.5 V, TA = 25 C, unless otherwise noted.)
Min Typ 1 4 Max 6 7 60 100 1,000 30 50 500 3 Unit mV mV pA pA pA pA pA pA V dB dB V/mV V/mV V/mV mV/C fA/C fA/C fA/C V V mV mV mA mA W dB dB mA mA V/ms ms kHz Degrees nV//Hz nV//Hz pA//Hz
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current
Symbol VOS IB IOS
Conditions
-40C TA +125C -40C TA +85C -40C TA +125C -40C TA +85C -40C TA +125C VCM = 0 V to 3 V -40C TA +125C RL = 100 kW , VO = 0.5 V to 2.2 V -40C TA +85C -40C TA +125C -40C TA +125C -40C TA +85C -40C TA +125C -40C TA +125C IL = 1 mA -40C TA +125C IL = 1 mA -40C TA +125C VOUT = VS - 1 V f = 200 kHz, AV = 1 VS = 2.5 V to 6 V -40C TA +125C VO = 0 V -40C TA +125C RL = 100 kW To 0.01% (1 V Step) 65 60
Input Offset Current
0.1
Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain
CMRR AVO DVOS /DT DIB /DT DIOS /DT VOH VOL IOUT ISC ZOUT PSRR ISY
0 40 38 100 50 2
45 500
Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Density Current Noise Density
Specifications subject to change without notice.
4 100 2,000 25 2.875 2.850 2.955 32 18 25 50 76 40 60 75 100 125
SR tS GBP Fo en en in
0.4
0.8 5 980 64 42 38 <0.1
f = 1 kHz f = 10 kHz
REV. D
-3-
AD8541/AD8542/AD8544-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V = 5.0 V, V
S CM
= 2.5 V, TA = 25 C, unless otherwise noted.)
Min Typ 1 4 Max 6 7 60 100 1,000 30 50 500 5 Unit mV mV pA pA pA pA pA pA V dB dB V/mV V/mV V/mV mV/C fA/C fA/C fA/C V V mV mV mA mA W dB dB mA mA V/ms kHz ms kHz Degrees nV//Hz nV//Hz pA//Hz
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current
Symbol VOS IB IOS
Conditions
-40C TA +125C -40C TA +85C -40C TA +125C -40C TA +85C -40C TA +125C VCM = 0 V to 5 V -40C TA +125C RL = 100 kW , VO = 0.5 V to 2.2 V -40C TA +85C -40C TA +125C -40C TA +125C -40C TA +85C -40C TA +125C -40C TA +125C IL = 1 mA -40C TA +125C IL = 1 mA -40C TA +125C VOUT = VS - 1 V f = 200 kHz, AV = 1 VS = 2.5 V to 6 V -40C TA +125C VO = 0 V -40C TA +125C RL = 100 kW, CL = 200 pF 1% Distortion To 0.1% (1 V Step) 65 60
Input Offset Current
0.1
Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain
CMRR AVO DVOS /DT DIB /DT DIOS /DT VOH VOL IOUT ISC ZOUT PSRR ISY
0 40 38 20 10 2
48 40
Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Density Current Noise Density
Specifications subject to change without notice.
4 100 2,000 25 4.9 4.875 4.965 25 30 60 45 76 45 65 85 100 125
SR BWP tS GBP Fo en en in
0.45
0.92 70 6 1,000 67 42 38 <0.1
f = 1 kHz f = 10 kHz
-4-
REV. D
AD8541/AD8542/AD8544
ABSOLUTE MAXIMUM RATINGS 1 PACKAGE INFORMATION
Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . 6 V Storage Temperature Range . . . . . . . . . . . . -65C to +150C Operating Temperature Range . . . . . . . . . . -40C to +125C Junction Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 60 sec) . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 For supplies less than 6 V, the differential input voltage is equal to VS.
Package Type 5-Lead SC70 (KS) 5-Lead SOT-23 (RT) 8-Lead SOIC (R) 8-Lead MSOP (RM) 8-Lead TSSOP (RU) 14-Lead SOIC (R) 14-Lead TSSOP (RU)
JA*
JC
Unit C/W C/W C/W C/W C/W C/W C/W
376 230 158 210 240 120 240
126 146 43 45 43 36 43
*qJA is specified for worst-case conditions, i.e., JA is specified for device soldered onto a circuit board for surface mount packages.
ORDERING GUIDE
Model AD8541AKS-R2 AD8541AKS-REEL7 AD8541AKSZ-REEL7* AD8541AR AD8541AR-REEL AD8541AR-REEL7 AD8541ART-R2 AD8541ART-REEL AD8541ART-REEL7 AD8541ARTZ-REEL* AD8541ARTZ-REEL7* AD8542AR AD8542AR-REEL AD8542AR-REEL7 AD8542ARZ* AD8542ARZ-REEL* AD8542ARZ-REEL7* AD8542ARM-R2 AD8542ARM-REEL AD8542ARU AD8542ARU-REEL AD8542ARUZ* AD8542ARUZ-REEL* AD8544AR AD8544AR-REEL AD8544AR-REEL7 AD8544ARZ* AD8544ARZ-REEL* AD8544ARZ-REEL7* AD8544ARU AD8544ARU-REEL AD8544ARUZ* AD8544ARUZ-REEL*
*Z = Pb-free part.
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 5-Lead SC70 5-Lead SC70 5-Lead SC70 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead MSOP 8-Lead MSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 14-Lead SOIC 14-Lead SOIC 14-Lead SOIC 14-Lead SOIC 14-Lead SOIC 14-Lead SOIC 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP
Package Option KS-5 KS-5 KS-5 R-8 R-8 R-8 RT-5 RT-5 RT-5 RT-5 RT-5 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RU-8 RU-8 RU-8 RU-8 R-14 R-14 R-14 R-14 R-14 R-14 RU-14 RU-14 RU-14 RU-14
Branding Information A4B A4B A4B
A4A A4A A4A A4A A4A
AVA AVA
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8541/AD8542/AD8544 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
-5-
AD8541/AD8542/AD8544 -Typical Performance Characteristics
180 160 INPUT OFFSET VOLTAGE - mV 140 120 100 80 60 40 20 0 4.5 3.5 2.5 1.5 0.5 0.5 1.5 2.5 3.5 4.5 INPUT OFFSET VOLTAGE - mV
INPUT BIAS CURRENT - pA
NUMBER OF AMPLIFIERS
VS = 5V VCM = 2.5V TA = 25 C
1.0 VS = 2.7V AND 5V 0.5 VCM = VS /2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 55 35 15 5 25 45 65 85 105 125 145 TEMPERATURE - C
9
VS = 2.7V AND 5V 8 VCM = VS /2 7 6 5 4 3 2 1 0 0.5 0.5 1.5 2.5 3.5 4.5 COMMON-MODE VOLTAGE - V 5.5
TPC 1. Input Offset Voltage Distribution
TPC 2. Input Offset Voltage vs. Temperature
TPC 3. Input Bias Current vs. Common-Mode Voltage
400 350
INPUT BIAS CURRENT - pA
POWER SUPPLY REJECTION - dB
VS = 2.7V AND 5V VCM = VS /2
INPUT OFFSET CURRENT - pA
7 6 5 4 3 2 1 0
VS = 2.7V AND 5V VCM = VS /2
160 140 120 100 80 60 40 20 0 20 40 100 1k 10k 100k FREQUENCY - Hz 1M 10M +PSRR PSRR VS = 2.7V TA = 25 C
300 250 200 150 100 50 0
40
20
0
20 40 60 80 100 120 140 TEMPERATURE - C
1
55
35
15 5 25 45 65 85 105 125 145 TEMPERATURE - C
TPC 4. Input Bias Current vs. Temperature
TPC 5. Input Offset Current vs. Temperature
TPC 6. Power Supply Rejection Ratio vs. Frequency
10k VS = 2.7V TA = 25 C
OUTPUT VOLTAGE - mV
3.0 VS = 2.7V VIN = 2.5V p-p RL = 2k TA = 25 C
60 VS = 2.7V RL = TA = 25 C
1k
SMALL SIGNAL OVERSHOOT - %
2.5
50
OUTPUT SWING - V p-p
100 SOURCE 10 SINK 1
2.0
40 +OS 30 OS
1.5
1.0
20
0.1 0.01 0.001
0.5
10 0 10
0.01
0.1 1 10 LOAD CURRENT - mA
100
0 1k
10k
100k 1M FREQUENCY - Hz
10M
100 1k CAPACITANCE - pF
10k
TPC 7. Output Voltage to Supply Rail vs. Load Current
TPC 8. Closed-Loop Output Voltage Swing vs. Frequency
TPC 9. Small Signal Overshoot vs. Load Capacitance
-6-
REV. D
AD8541/AD8542/AD8544
60
SMALL SIGNAL OVERSHOOT - % SMALL SIGNAL OVERSHOOT - %
60 VS = 2.7V RL = 10k TA = 25 C VS = 2.7V RL = 2k TA = 25 C
VS = 2.7V RL = 100kV CL = 300pF AV = 1 TA = 25 C
50
50
40 +OS 30 OS
40 +OS OS 20
30
1.35V
20
10 0 10
10 0 10
50mV 10 s
100 1k CAPACITANCE - pF
10k
100 1k CAPACITANCE - pF
10k
TPC 10. Small Signal Overshoot vs. Load Capacitance
TPC 11. Small Signal Overshoot vs. Load Capacitance
TPC 12. Small Signal Transient Response
VS = 2.7V RL = NO LOAD TA = 25 C 80 45 90 135 180
POWER SUPPLY REJECTION RATIO - dB
160 140 120 100 80 60 +PSRR 40 20 0 20 40 100 1k 10k 100k FREQUENCY - Hz 1M 10M PSRR VS = 5V TA = 25 C
GAIN - dB
60 40 20 0
1.35V VS = 2.7V RL = 2k AV = 1 TA = 25 C 500mV 10 s
1k
10k
100k 1M FREQUENCY - Hz
10M
TPC 13. Large Signal Transient Response
TPC 14. Open-Loop Gain and Phase vs. Frequency
PHASE SHIFT - Degrees
TPC 15. Power Supply Rejection Ratio vs. Frequency
90
COMMON-MODE REJECTION - dB
10k VS = 5V TA = 25 C OUTPUT VOLTAGE - mV VS = 5V TA = 25 C OUTPUT SWING - V p-p
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VS = 5V VIN = 4.9V p-p RL = NO LOAD TA = 25 C
80 70 60 50 40 30 20 10 0 10 1k
1k 100
SOURCE 10 SINK 1
0.1 0.01 0.001
10k
100k 1M FREQUENCY - Hz
10M
0.01
0.1 1 10 LOAD CURRENT - mA
100
0 1k
10k
100k 1M FREQUENCY - Hz
10M
TPC 16. Common-Mode Rejection Ratio vs. Frequency
TPC 17. Output Voltage to Supply Rail vs. Frequency
TPC 18. Closed-Loop Output Voltage Swing vs. Frequency
REV. D
-7-
AD8541/AD8542/AD8544
5.0
SMALL SIGNAL OVERSHOOT - %
60 SMALL SIGNAL OVERSHOOT - %
VS = 5V VIN = 4.9V p-p RL = 2k TA = 25 C
60
4.5 4.0
50
OUTPUT SWING - V p-p
VS = 5V RL = 10k TA = 25 C
50
VS = 5V RL = 2k TA = 25 C
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1k 10k
40 +OS 30 OS
40 +OS OS 20
30
20
10 0 10
10 0 10
100k 1M FREQUENCY - Hz
10M
100 1k CAPACITANCE - pF
10k
100 1k CAPACITANCE - pF
10k
TPC 19. Closed-Loop Output Voltage Swing vs. Frequency
TPC 20. Small Signal Overshoot vs. Load Capacitance
TPC 21. Small Signal Overshoot vs. Load Capacitance
60
SMALL SIGNAL OVERSHOOT - %
50
VS = 5V RL = TA = 25 C
40 +OS 30 OS 20
VS = 5V RL = 100k CL = 300pF AV = 1 TA = 25 C
2.5V
2.5V VS = 5V RL = 2k AV = 1 TA = 25 C
50mV 10 s
10 0 10
1V
10 s
100 1k CAPACITANCE - pF
10k
TPC 22. Small Signal Overshoot vs. Load Capacitance
TPC 23. Small Signal Transient Response
TPC 24. Large Signal Transient Response
PHASE SHIFT - Degrees
80
45 90 135 180
SUPPLY CURRENT/AMPLIFIER -
VS = 5V RL = NO LOAD TA = 25 C
VIN
VS = 5V RL = 10k AV = 1 TA = 25 C
60
A
TA = 25 C 50
40
GAIN - dB
60 40 20 0
VOUT 2.5V
30
20
10
1V
1k 10k 100k 1M FREQUENCY - Hz 10M
20 s
0
0
1
2 3 4 SUPPLY VOLTAGE - V
5
6
TPC 25. Open-Loop Gain and Phase vs. Frequency
TPC 26. No Phase Reversal
TPC 27. Supply Current per Amplifier vs. Supply Voltage
-8-
REV. D
AD8541/AD8542/AD8544
55
1,000 VS = 2.7V AND 5V AV = 1 800 TA = 25 C 900 700 VS = 5V AV = 1 MARKER SET @ 10kHz MARKER READING: 37.6 V/ Hz TA = 25 C
200mV/DIVISION
SUPPLY CURRENT/AMPLIFIER - A
50 VS = 5V 45 40 VS = 2.7V 35 30 25
IMPEDANCE -
600 500 400 300 200 100
20 55 35 15 5 25 45 65 85 105 125 145 TEMPERATURE - C
0 1k
10k
100k 1M FREQUENCY - Hz
10M
100M
0
5
10 15 FREQUENCY - kHz
20
25
TPC 28. Supply Current per Amplifier vs. Temperature
TPC 29. Closed-Loop Output Impedance vs. Frequency
TPC 30. Voltage Noise
NOTES ON THE AD854x AMPLIFIERS
The AD8541/AD8542/AD8544 amplifiers are improved performance general-purpose operational amplifiers. Performance has been improved over previous amplifiers in several ways.
Lower Supply Current for 1 MHz Gain Bandwidth
The AD854x series typically uses 45 mA of current per amplifier. This is much less than the 200 mA to 700 mA used in earlier generation parts with similar performance. This makes the AD854x series a good choice for upgrading portable designs for longer battery life. Alternatively, additional functions and performance can be added at the same current drain.
Higher Output Current
drift will cause the circuit to no longer attenuate at the ideal notch frequency. To achieve desired performance, 1% or better component tolerances or special component screens are usually required. One method to desensitize the circuitto-component mismatch is to increase R2 with respect to R1, which lowers Q. A lower Q increases attenuation over a wider frequency range but reduces attenuation at the peak notch frequency.
5.0V R 100k C2 53.6 F R/2 50k 2.5VREF C 26.7nF C 26.7nF R2 2.5k 5 6 R1 97.5k 1 R1 R1+R2 R 100k 3 2 8 U1 4
1/2 AD8542
1
V OUT
At 5 V single supply, the short-circuit current is typically 60 mA. Even 1 V from the supply rail, the AD854x amplifiers can provide 30 mA, sourcing or sinking. Sourcing and sinking are strong at lower voltages, with 15 mA available at 2.7 V and 18 mA at 3.0 V. For even higher output currents, please see the Analog Devices AD8531/AD8532/AD8534 parts, with output currents to 250 mA. Information on these parts is available from your Analog Devices representative, and data sheets are available at the Analog Devices website at www.analog.com.
Better Performance at Lower Voltages
1/2 AD8542
7 U2
f0 = f0 =
1 2pRC
41
[
]
5.0V R 3 2 7
2.5VREF
The AD854x family of parts has been designed to provide better ac performance, at 3.0 V and 2.7 V, than previously available parts. Typical gain-bandwidth product is close to 1 MHz at 2.7 V. Voltage gain at 2.7 V and 3.0 V is typically 500,000. Phase margin is typically over 60C, making the part easy to use.
VIN
Figure 1. 60 Hz Twin-T Notch Filter, Q = 10
R
AD8541
4 6
V OUT
2C
APPLICATIONS Notch Filter
The AD8542 has very high open-loop gain (especially with a supply voltage below 4 V), which makes it useful for active filters of all types. For example, Figure 1 illustrates the AD8542 in the classic Twin-T Notch Filter design. The Twin-T Notch is desired for simplicity, low output impedance, and minimal use of op amps. In fact, this notch filter may be designed with only one op amp if Q adjustment is not required. Simply remove U2 as illustrated in Figure 2. However, a major drawback to this circuit topology is ensuring that all the Rs and Cs closely match. The components must closely match or notch frequency offset and REV. D -9-
2.5VREF C
R/2
C
Figure 2. 60 Hz Twin-T Notch Filter, Q = * (Ideal)
Figure 3 shows another example of the AD8542 in a notch filter circuit. The FNDR notch filter has fewer critical matching requirements than the Twin-T Notch and for the FNDR Q is directly proportional to a single resistor R1. While matching component values is still important, it is also
AD8541/AD8542/AD8544
much easier and/or less expensive to accomplish in the FNDR circuit. For example, the Twin-T notch uses three capacitors with two unique values, whereas the FNDR circuit uses only two capacitors, which may be of the same value. U3 is simply a buffer that is added to lower the output impedance of the circuit.
R1 Q ADJUST 200 C1 1F R 2.61k C2 1F R 2.61k R 2.61k 1 2p LC1 R2C2 R 2.61k 2.5VREF 13 12 3 2 4 U1 11 9 10
Photodiode Application
1/4 AD8544
U3 8
The AD854x family has very high impedance with input bias current typically around 4 pA. This characteristic allows the AD854x op amps to be used in photodiode applications and other applications that require high input impedance. Note that the AD854x has significant voltage offset, which can be removed by capacitive coupling or software calibration. Figure 5 illustrates a photodiode or current measurement application. The feedback resistor is limited to 10 MW to avoid excessive output offset. Also, note that a resistor is not needed on the noninverting input to cancel bias current offset because the bias current related output offset is not significant when compared to the voltage offset contribution. For the best performance follow the standard high impedance layout techniques including: Shield the circuit. Clean the circuit board. Put a trace connected to the noninverting input around the inverting input.
V OUT
2.5VREF
1/4 AD8544
1
1/4 AD8544
7 U2
6 5
1/4 AD8544
U4 14 NC SPARE
f=
Use separate analog and digital power supplies.
C 100pF R 10M V+ OR 2 3 D 4 7 6 V OUT
L=
2.5VREF
Figure 3. FNDR 60 Hz Notch Filter with Output Buffer
Comparator Function
A comparator function is a common application for a spare op amp in a quad package. Figure 4 illustrates 1/4 of the AD8544 as a comparator in a standard overload detection application. Unlike many op amps, the AD854x family can double as comparators because this op amp family has rail-to-rail differential input range, rail-to-rail output, and a great speed versus power ratio. R2 is used to introduce hysteresis. The AD854x, when used as comparators, have 5 ms propagation delay at 5 V and 5 ms overload recovery time.
R2 1M R1 1k
AD8541
2.5VREF
2.5VREF
Figure 5. High Input Impedance Application-Photodiode Amplifier
V OUT
VIN 2.5VDC 2.5VREF
1/4 AD8544
Figure 4. AD854x Comparator Application-Overload Detector
-10-
REV. D
AD8541/AD8542/AD8544
* AD8542 SPICE Macro-model Typical Values * 6/98, Ver. 1 * TAM / ADSC * * Copyright 1998 by Analog Devices * * Refer to "README.DOC" file for License * Statement. Use of this model indicates your * acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * || positive supply * || | negative supply * || | | output * || ||| * || ||| .SUBCKT AD8542 1 2 99 50 45 * * INPUT STAGE * M1 4 1 8 8 PIX L=0.6E-6 W=16E-6 M2 6 7 8 8 PIX L=0.6E-6 W=16E-6 M3 11 1 10 10 NIX L=0.6E-6 W=16E-6 M4 12 7 10 10 NIX L=0.6E-6 W=16E-6 RC1 4 50 20E3 RC2 6 50 20E3 RC3 99 11 20E3 RC4 99 12 20E3 C1 4 6 1.5E-12 C2 11 12 1.5E-12 I1 99 8 1E-5 I2 10 50 1E-5 V1 99 9 0.2 V2 13 50 0.2 D1 8 9 DX D2 13 10 DX EOS 7 2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1 IOS 1 2 2.5E-12 * * CMRR 64dB, ZERO AT 20kHz * ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 21 22 79.6E3 CCM1 21 22 100E-12 RCM2 22 98 50 * * PSRR=90dB, ZERO AT 200Hz * RPS1 70 0 1E6 RPS2 71 0 1E6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 1.59E6 CPS3 72 73 500E-12 RPS4 73 98 25 * * VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz) * VN1 80 0 0 RN1 80 0 16.45E-3 HN 81 0 VN1 35 RN2 81 0 1 * * INTERNAL VOLTAGE REFERENCE * VFIX 90 98 DC 1 S1 90 91 (50,99) VSY_SWITCH VSN1 91 92 DC 0 RSY 92 98 1E3 EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 POLY(1) (99,50) 0 3.7E-6 * * ADAPTIVE GAIN STAGE * AT Vsy>+4.2, AVol=45 V/mv * AT Vsy<+3.8, AVol=450 V/mv * G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5 VR1 30 31 DC 0 H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9 CF 45 30 10E-12 D3 30 99 DX D4 50 30 DX * * OUTPUT STAGE * M5 45 46 99 99 POX L=0.6E-6 W=375E-6 M6 45 47 50 50 NOX L=0.6E-6 W=500E-6 EG1 99 46 POLY(1) (98,30) 1.05 1 EG2 47 50 POLY(1) (30,98) 1.04 1 * * MODELS * .MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=+1,LAMBDA=0.067) .MODEL NOX NMOS (LEVEL=2,KP=20E+6,VTO=1,LAMBDA=0.067) .MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=+0.7,LAMBDA=0.01,KF=1E-31) .MODEL NIX NMOS (LEVEL=2,KP=20E+6,VTO=0.7,LAMBDA=0.01,KF=1E-31) .MODEL DX D(IS=1E-14) .MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=+4.2,VON=-3.5) .ENDS AD8542
REV. D
-11-
AD8541/AD8542/AD8544
OUTLINE DIMENSIONS 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8)
Dimensions shown in millimeters
14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
Dimensions shown in millimeters
3.10 3.00 2.90
5.10 5.00 4.90
8
5
14
8
4.50 4.40 6.40 BSC 4.30
1 4
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 1.20 MAX SEATING 0.20 PLANE 0.09 8 0
PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19
0.20 0.09 8 0
0.30 COPLANARITY 0.19 0.10
0.75 0.60 0.45
SEATING COPLANARITY PLANE 0.10
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153AA
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968) 4.80 (0.1890)
8 5 4
14-Lead Standard Small Outline Package [SOIC] Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 3.80 (0.1496)
14 1 8 7
4.00 (0.1574) 3.80 (0.1497)
1
6.20 (0.2440) 5.80 (0.2284)
6.20 (0.2441) 5.80 (0.2283)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE
1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.17 (0.0067)
0.50 (0.0196) 0.25 (0.0099)
45
0.25 (0.0098) 0.10 (0.0039)
1.27 (0.0500) BSC
1.75 (0.0689) 1.35 (0.0531)
0.50 (0.0197) 0.25 (0.0098)
45
0.51 (0.0201) 0.31 (0.0122)
1.27 (0.0500) 0.40 (0.0157)
COPLANARITY 0.10
0.51 (0.0201) 0.31 (0.0122)
SEATING PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
-12-
REV. D
AD8541/AD8542/AD8544
OUTLINE DIMENSIONS 8-Lead Mini Small Outline Package [MSOP] (RM-8)
Dimensions shown in millimeters
5-Lead Small Outline Transistor Package [SOT-23] (RT-5)
Dimensions shown in millimeters
3.00 BSC
2.90 BSC
8
5
5
4
3.00 BSC
1 4
4.90 BSC
1.60 BSC
1 2 3
2.80 BSC
PIN 1 0.65 BSC 0.15 0.00 0.38 0.22 COPLANARITY 0.10 1.10 MAX 8 0 0.80 0.60 0.40 1.30 1.15 0.90
PIN 1 0.95 BSC 1.90 BSC
0.23 0.08 SEATING PLANE
1.45 MAX
0.22 0.08 10 5 0 0.60 0.45 0.30
0.15 MAX
COMPLIANT TO JEDEC STANDARDS MO-187AA
0.50 0.30
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AA
5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5)
Dimensions shown in millimeters
2.00 BSC
5
4
1.25 BSC
1 2 3
2.10 BSC
PIN 1 1.00 0.90 0.70 0.65 BSC 1.10 MAX 0.22 0.08 0.30 0.15 0.10 COPLANARITY SEATING PLANE 0.46 0.36 0.26
0.10 MAX
COMPLIANT TO JEDEC STANDARDS MO-203AA
REV. D
-13-
AD8541/AD8542/AD8544 Revision History
Location 8/04--Data Sheet changed from REV. C to REV. D. Page
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Change to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1/03--Data Sheet changed from REV. B to REV. C.
Updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Change to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
-14-
REV. D
-15-
-16-
C00935-0-8/04(D)

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